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cmos-ccd 1h/2h delay line for pal description the cxl1506m/n is a cmos-ccd delay line developed for video signal processing. usage in conjunction with an external low pass filter provides 1h and 2h delay signals simultaneously (for pal signals). features single power supply (5v) low power consumption built-in peripheral circuits built-in tripling pll circuit for pal signals 1 input and 2 outputs (outputs for both 1h and 2h delays) absolute maximum ratings (ta = 25?) supply voltage v dd 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl1506m 400 mw cxl1506n 300 mw recommended operating voltage (ta = 25?) v dd 5 0.25 v recommended clock conditions (ta = 25?) input clock amplitude v clk 0.2 to 1.0vp-p (0.4vp-p typ.) input clock frequency f clk 4.433619 mhz input clock waveform sine wave input signal amplitude v sig 575 (max.) mvp-p (at internal clamp condition) ?1 e89x22c78-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl1506m/n cxl1506m 16 pin sop (plastic) cxl1506n 20 pin ssop (plastic) blook diagram cxl1506m cxl1506n autobias circuit driver bias circuit pll timing ccd (1698bits) clamp circuit output circuit s/h 1bit aa aa 14 12 13 10 11 2 5 6 7 1 v ss v dd vco in pc out v ss in vg1 vg2 out1 (1h) v ss out2 (2h) 8 clk v ss (vco out) 15 16 ab v dd v ss output circuit s/h 1bit 9 4 847bits 1698bits 3 autobias circuit driver bias circuit pll timing ccd (1698bits) clamp circuit output circuit s/h 1bit aa aa 14 12 13 10 11 2 5 6 7 1 v ss nc v dd vco in pc out v ss in vg1 vg2 out1 (1h) v ss out2 (2h) 8 clk v ss (vco out) nc 15 16 17 18 19 20 ab v dd nc nc v ss output circuit s/h 1bit 9 4 847bits 1698bits 3
? 2 cxl1506m/n pin description (cxl1506m) pin no. symbol i/o description impedance [ ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 in vg1 vg2 out1 v ss out2 v ss (vco out) v ss v dd clk v ss pc out vco in v dd ab v ss i o i o o (o) i o i o signal input (non-inverted signal) gate bias 1 dc output gate bias 2 dc input 1h signal output (inverted signal) gnd 2h signal output (inverted signal) gnd or vco output (3fsc) gnd power supply (5v) clock input (fsc) gnd phase comparator output vco input power supply (5v) autobias dc output gnd > 10k (at no clamp) 40 to 500 40 to 500 > 10k 600 to 200k note) description of vg2 control of input signal clamp condition 0v sync tip clamp condition 5v center bias condition the input signal is biased to approx. 2.1v by means of the ic internal resistance (approx. 10k ). in this mode the input signal is limited to the apl 50% and the maximum input signal amplitude is at 200mvp-p. (note)
? 3 cxl1506m/n pin description (cxl1506n) pin no. symbol i/o description impedance [ ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 nc in vg1 vg2 out1 v ss out2 nc v ss (vco out) v ss v dd clk nc v ss pc out vco in v dd ab nc v ss i o i o o (o) i o i o signal input (non-inverted signal) gate bias 1 dc output gate bias 2 dc input 1h signal output (inverted signal) gnd 2h signal output (inverted signal) gnd or vco output (3fsc) gnd power supply (5v) clock input (fsc) gnd phase comparator output vco input power supply (5v) autobias dc output gnd > 10k (at no clamp) 40 to 500 40 to 500 > 10k 600 to 200k note) description of vg2 control of input signal clamp condition 0v sync tip clamp condition 5v center bias condition the input signal is biased to approx. 2.1v by means of the ic internal resistance (approx. 10k ). in this mode the input signal is limited to the apl 50% and the maximum input signal amplitude is at 200mvp-p. (note)
? 4 cxl1506m/n electrical characteristics (ta = 25 c, v dd = 5v, f clk = 4.433619mhz, v clk = 400mvp-p sine wave) see electrical characteristics test circuit. item symbol test conditions (note 1) sw conditions min. typ. max. unit note 1 2 3 4 2 3 4 5 5 6 7 ma db db % degree db mvp-p 37 2 2 ?.7 ?.8 7 7 7 7 350 350 27 0 0 ?.7 ?.8 5 5 5 5 56 56 17 ? ? ?.7 ?.8 52 52 a b b b b c c c c d d a a a a b a b a b a b a b a b b b b a a b b b b b b b b a a a b ? ? c b ? ? c d d d d e e e e 200khz 500mvp-p sine wave 200khz ? ? 4.434mhz 150mvp-p sine wave 5 staircase wave 5 staircase wave no signal input no signal input i dd gl1 gl2 fr1 fr2 dg1 dg2 dp1 dp2 sn1 sn2 cp1 cp2 supply current low frequency gain frequency response differential gain differential phase s/n ratio s/h pulse coupling
? 5 cxl1506m/n 1 3 . 3 m 1 3 . 3 m 0 3 . 3 v s s a b v d d v c o i n p c o u t v d d c l k 1 0 0 0 p 1 2 0 3 . 3 8 2 k 1 c l k f s c ( 4 . 4 3 3 6 1 9 m h z ) , 4 0 0 m v p - p s i n e w a v e i n v g 1 v g 2 o u t 1 v s s v s s ( v c o o u t ) v s s a b 1 m 1 2 0 0 k h z 5 0 0 m v p - p s i n e w a v e 2 0 0 k h z 1 5 0 m v p - p s i n e w a v e 4 . 4 3 4 m h z 1 5 0 m v p - p s i n e w a v e 5 - s t a i r c a s e w a v e a b d a s w 4 2 3 4 5 6 7 1 b c d n o t e 1 ) n o t e 2 ) l p f b p f n o t e 1 ) l p f f r e q u e n c y r e s p o n s e 0 3 5 0 6 m f - f r e q u e n c y [ h z ] [ d b ] n o t e 2 ) b p f f r e q u e n c y r e s p o n s e 0 3 5 0 6 m f - f r e q u e n c y [ h z ] [ d b ] 2 0 0 8 9 1 1 1 3 1 4 s w 1 s w 3 1 5 1 6 o u t 2 v s s 1 0 1 2 a 0 . 1 1 0 0 0 p 1 0 0 0 p a b c 5 v 1 0 0 0 p s w 2 0 e 0 . 1 s p e c t r u m a n a l y z e r v e c t o r s c o p e n o i s e m e t e r o s c i l l o s c o p e electrical characteristics test circuit (cxl1506m) * when using cxl1506n, change the connection terminal only. (see the block diagram and pin configuration. for nc pins, ground them.)
? 6 cxl1506m/n 2) this is the ic supply current value during clock and signal input. 3) gl is the output gain of pin out when a 500mvp-p, 200khz sine wave is fed to pin in. gl = 20 log [db] 4) indicates the dissipation at 4.434mhz in relation to 200khz. from the output voltage at pin out when a 150mvp-p, 200khz sine wave is fed to pin in, and from the output voltage at pin out when a 150mvp-p, 4.434mhz sine wave is fed to same, calculation is made according to the following formula. fr = 20 log [db] 5) the differential gain (dg) and the differential phase (dp), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: pin out output voltage [mvp-p] 500 [mvp-p] pin out output voltage (4.434mhz) [mvp-p] pin out output voltage (200khz) [mvp-p] 1 h 6 4 s 1 5 0 m v 2 7 5 m v 5 0 0 m v 1 5 0 m v notes) 1) by switching sw2, input condition turns out as follows. sw2 condition input condition a b center bias condition (approx. 2.1v) approx. 2.1v bias is applied internally to the input signal sync tip and clamp conditions
? 7 cxl1506m/n gl 20 6) the noise level of the output signal at no-input signal is tested with a video noise meter in the sub carrier trap mode at bpf 100khz to 5mhz. (vn [vrms]) the signal component is determined either by testing the output voltage (the same testing system as for noise level) at the input of 350mvp-p, 200khz, or by utilizing values from gl to calculate according to the following formula. (vs [vp-p]) (example of vs calculation) vs = 0.35 10 (example of sn ratio calculation) sn = 20 log [db] 7) the internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. clock vn (noise component) [vrms] vs (signal component) [vp-p] t e s t v a l u e [ m v p - p ] 4 0 0 m v p - p ( t y p . ) f s c ( 4 . 4 3 3 6 1 9 m h z ) s i n e w a v e
? 8 cxl1506m/n application circuit (cxl1506m) 3 . 3 1 0 0 0 p 1 2 0 3 . 3 8 2 k 1 c l k f s c ( 4 . 4 3 3 6 1 9 m h z ) , 4 0 0 m v p - p s i n e w a v e 1 m 2 3 4 5 6 7 1 8 9 1 1 1 3 1 4 1 0 0 1 5 1 6 1 2 0 . 1 1 0 0 0 p 1 0 0 0 p 5 v 1 0 0 0 p 0 . 1 4 7 0 3 3 0 k 5 6 0 k 1 k 6 2 p l p f 2 . 2 k 2 . 2 k 2 . 2 k 5 v t r a n s i s t o r u s e d p n p : 2 s a 1 1 7 5 t r a n s i s t o r u s e d n p n : 2 s c 4 0 3 1 h o u t p u t ( n o n - i n v e r t e d s i g n a l ) 0 . 1 1 0 0 4 7 0 3 3 0 k 5 6 0 k 1 k 6 2 p l p f 2 . 2 k 2 . 2 k 2 . 2 k 5 v t r a n s i s t o r u s e d p n p : 2 s a 1 1 7 5 t r a n s i s t o r u s e d n p n : 2 s c 4 0 3 2 h o u t p u t 0 . 1 v 1 ( i n v e r t e d s i g n a l ) ( n o n - i n v e r t e d s i g n a l ) s i g n a l i n p u t ( n o n - i n v e r t e d s i g n a l ) ( i n v e r t e d s i g n a l ) d e l a y t i m e 2 3 0 n s c x l 1 5 0 6 m 1 0 1 a a a a a a a * w h e n u s i n g c x l 1 5 0 6 n , c h a n g e t h e c o n n e c t i o n t e r m i n a l o n l y . ( s e e t h e b l o c k d i a g r a m a n d p i n c o n f i g u r a t i o n . f o r n c p i n s , g r o u n d t h e m . ) 2 s c 4 0 3 3 f s c o u t 1 . 8 k 1 . 8 k 5 v 7 n o t e ) w h e n v c o o u t i s r e q u i r e d , u s e t h e c i r c u i t b e l o w . d e l a y t i m e 2 1 0 n s n o t e ) w h e n u s i n g p i n 7 ( v c o o u t ) , u s e t h e c i r c u i t a s s h o w n b e l o w . w h e n n o t u s i n g i t , g n d . application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 9 cxl1506m/n example of representative characteristics l o w f r e q u e n c y g a i n ( 1 h ) v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 2 1 0 1 2 a m b i e n t t e m p e r a t u r e [ c ] l o w f r e q u e n c y g a i n 1 h [ d b ] s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 1 5 3 5 2 5 a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t [ m a ] l o w f r e q u e n c y g a i n ( 2 h ) v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 0 1 2 a m b i e n t t e m p e r a t u r e [ c ] l o w f r e q u e n c y g a i n 2 h [ d b ] d i f f e r e n t i a l g a i n ( 1 h ) v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 2 4 6 8 1 0 0 a m b i e n t t e m p e r a t u r e [ c ] d i f f e r e n t i a l g a i n 1 h [ % ] 2 1 f r e q u e n c y r e s p o n s e ( 1 h ) v s . a m b i e n t t e m p e r a t u r e 2 1 0 3 a m b i e n t t e m p e r a t u r e [ c ] f r e q u e n c y r e s p o n s e 1 h [ d b ] 2 0 0 2 0 4 0 6 0 8 0 f r e q u e n c y r e s p o n s e ( 2 h ) v s . a m b i e n t t e m p e r a t u r e 2 1 0 3 a m b i e n t t e m p e r a t u r e [ c ] f r e q u e n c y r e s p o n s e 2 h [ d b ] 2 0 0 2 0 4 0 6 0 8 0
? 10 cxl1506m/n s u p p l y c u r r e n t v s . s u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 1 5 3 5 2 5 s u p p l y v o l t a g e [ v ] s u p p l y c u r r e n t [ m a ] l o w f r e q u e n c y g a i n ( 1 h ) v s . s u p p l y v o l t a g e 0 1 2 s u p p l y v o l t a g e [ v ] l o w f r e q u e n c y g a i n 1 h [ d b ] d i f f e r e n t i a l g a i n ( 2 h ) v s . a m b i e n t t e m p e r a t u r e 2 0 0 2 0 4 0 6 0 8 0 2 4 6 8 1 0 0 a m b i e n t t e m p e r a t u r e [ c ] d i f f e r e n t i a l g a i n 2 h [ % ] 2 1 f r e q u e n c y r e s p o n s e ( 2 h ) v s . s u p p l y v o l t a g e 2 1 0 3 s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e 2 h [ d b ] f r e q u e n c y r e s p o n s e ( 1 h ) v s . s u p p l y v o l t a g e 2 1 0 3 s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e 1 h [ d b ] l o w f r e q u e n c y g a i n ( 2 h ) v s . s u p p l y v o l t a g e 0 1 2 s u p p l y v o l t a g e [ v ] l o w f r e q u e n c y g a i n 2 h [ d b ] 2 1 4 . 7 5 5 5 . 2 5 4 . 7 5 5 5 . 2 5 4 . 7 5 5 5 . 2 5 4 . 7 5 5 5 . 2 5
? 11 cxl1506m/n d i f f e r e n t i a l g a i n ( 1 h ) v s . s u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 2 4 6 8 1 0 0 s u p p l y v o l t a g e [ v ] d i f f e r e n t i a l g a i n 1 h [ % ] d i f f e r e n t i a l g a i n ( 2 h ) v s . s u p p l y v o l t a g e 2 4 6 8 1 0 0 s u p p l y v o l t a g e [ v ] d i f f e r e n t i a l g a i n 2 h [ % ] 4 . 7 5 5 5 . 2 5 f r e q u e n c y r e s p o n s e ( 1 h ) 1 0 k 1 0 0 k 1 m 6 4 2 0 2 f r e q u e n c y [ h z ] g a i n [ d b ] 1 0 m f r e q u e n c y r e s p o n s e ( 2 h ) 1 0 k 1 0 0 k 1 m 6 4 2 0 2 f r e q u e n c y [ h z ] g a i n [ d b ] 1 0 m note) 1h and 2h shown in brackets indicate 1h and 2h outputs.
? 12 cxl1506m/n package outline unit: mm cxl1506m p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s s o n y c o d e e i a j c o d e j e d e c c o d e s o p - 1 6 p - l 0 1 s o p 0 1 6 - p - 0 3 0 0 c o p p e r a l l o y s o l d e r p l a t i n g e p o x y r e s i n 1 6 p i n s o p ( p l a s t i c ) 9 . 9 0 . 1 + 0 . 4 1 6 9 1 8 1 . 2 7 0 . 4 5 0 . 1 5 . 3 0 . 1 + 0 . 3 7 . 9 0 . 4 6 . 9 1 . 8 5 0 . 1 5 + 0 . 4 0 . 5 0 . 2 0 . 2 0 . 0 5 + 0 . 1 0 . 1 0 . 0 5 + 0 . 2 0 . 2 g 0 . 1 5 m 0 . 2 4 2 0 p i n s s o p ( p l a s t i c ) s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y 0 . 1 g s s o p - 2 0 p - l 0 1 s s o p 0 2 0 - p - 0 0 4 4 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a p l a t i n g * 6 . 5 0 . 1 * 4 . 4 0 . 1 0 . 2 2 0 . 0 5 + 0 . 1 0 . 6 5 2 0 1 1 1 0 1 a 0 . 1 + 0 . 0 5 1 . 2 5 0 . 1 + 0 . 2 0 . 1 5 0 . 0 2 6 . 4 0 . 2 n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 3 m cxl1506n

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